(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming solder bumps whereby plating is used to create Under Ball Metallurgy and printing is used for creating the solder ball.
(2) Description of the Prior Art
The present invention addresses a method of forming an electrical interconnection and, more particularly, a method of forming an interconnect bump. The method of the present invention can be used for the creation of electrical contacts on the surface of semiconductor devices but is not limited to such applications. The method of the present invention can equally be applied to form raised electrical contacts on semiconductor substrates, printed circuit boards, flex circuits or a metallized or glass substrate or semiconductor device mounting support. In its present form the method of the invention is most favorably applied to the creation of elevated points of electrical contact on the surface of semiconductor devices since this is the application where small size contact points with a diameter of 50 microns or less are of most benefit.
Past methods of forming electrical interconnects by forming elevated regions on a semiconductor surface used methods of electroplating or methods of screen-printing.
For the method of screen printing, where it is the objective to form elevated points of electrical contact on a semiconductor surface, a dry photoresist mask (referred to as a solder mask) is laminated over the semiconductor surface and patterned. The dry photoresist mask is left in place on the semiconductor surface where no elevated points of electrical contact are to be created, exposing the points of electrical contact over which the elevated points of electrical contact are to be created. A screen is used through which solder paste or flux is deposited onto the semiconductor surface where the elevated contact points are to be created, after which the bumps can be formed for electrical interconnect. The method of screen-printing is most typically used to create points of electrical contact (bumps) that have a diameter in excess of 100 microns. For device dimensions where smaller diameter bumps are required, another method must be provided that allows for the creation of smaller diameter bumps. For the dry resist method, the minimum thickness of the layer of dry photoresist is in the range of 75 to 100 microns, making it difficult to obtain openings of small diameter in the (relatively) thick layer of dry photoresist. For the application of the dry resist in the creation of bumps on the surface of a circuit board, the dry resist method has, up to this point, served its purpose. Where however smaller geometries are used, such as on the surface of a semiconductor device, the dry resist method does not provide for an interconnect bump with a small enough diameter. In addition, dry resist layers are difficult to apply and adhere to the surface of semiconductor substrates. The method of dry resist lamination can be further extended to create metal layers on the exposed portions of the underlying semiconductor surface by methods of electroplating. This too however runs into problems where small geometries are required for the to be created elevated point of electrical contact.
Other methods have been used to create the required pattern to form interconnect bumps. These methods have as objective to create, at the point where the interconnect bump has to be created, a surface that lends itself to this creation such as a surface containing a solderable material or a conductive polymer of a solder flux. A metal mask is for this purpose frequently used to shield areas, where no interconnect bumps are to be created, from the deposition of such materials. The metal mask presents problems of size limitations because the openings that can be created in the surface of the metal mask cannot be created small enough such that small enough diameter interconnect bumps can be created. In addition, masking techniques invariably present problems of alignment, these problems are further aggravated where very small geometries are required or where a dense pattern of interconnect bumps is to be created.
FIG. 1 shows an example of one of the methods that is used to create an interconnect bump. A semiconductor surface 10 has been provided with a metal contact pad 14, the semiconductor surface 10 is protected with a layer 12 of passivation. An opening 11 has been created in the layer 12 of passivation, the surface of the metal contact pad 12 is exposed through this opening 11. Next, FIG. 2, a dielectric layer 16 is deposited over the surface of the layer 12 of passivation, the layer 16 of dielectric is patterned and etched creating an opening 13 in the layer 16 of dielectric that aligns with the metal pad 14 and that partially exposes the surface of the metal pad 14. A layer 18 of metal, typically UBM, is created over the layer 16 of dielectric, layer 18 of metal is in contact with the surface of the metal pad 14 inside opening 13. The region of layer 18 of metal that is geometrically above the metal pad 14 will, at a later point in the processing, form a pedestal over which the interconnect bump will be formed. This pedestal can be further extended in a vertical direction by the deposition and patterning of one or more additional layers that may contain a photoresist or a dielectric material, these additional layers are not shown in FIG. 1. These layers essentially have the shape of layer 16 and are removed as one of the final processing steps that is applied for the formation of the interconnect bump.
A layer 20 of metal such as copper, FIG. 3, that forms an integral part of the to be created interconnect bump, is next electroplated on the surface of the layer 18 of metal, whereby the layer 18 serves as the lower electrode during the plating process. The final layer 22 of solder is electroplated on the surface of layer 20.
The layer 18 of metal is next etched, FIG. 4, leaving in place only the pedestal for the interconnect bump. During this etch process the deposited layers 20 and 22 serve as a mask. If, as indicated above, additional layers of dielectric or photoresist have been deposited for the further shaping of pedestal 18 in FIG. 4, these layers are also removed at this time.
A solder paste or flux is now applied to the layer 22 of solder, the solder 22 is melted in a reflow surface typically under a nitrogen atmosphere, creating the spherically shaped interconnect bump 22 that is shown in FIG. 4.
The above processing steps are in many of the applications of the indicated process augmented by processing steps of curing and pre-baking in order to improve hardness and other desirable performance parameters of the various layers that are used for the processing sequence that has been described in FIGS. 1 through 4. For instance, a layer of photoresist that is used as part of the processing sequence can be pre-baked prior to the exposure and etching of the photoresist layer. These steps have not been included in the above description for reasons of simplicity of description.
In addition to the above indicated additional layers of dielectric or photoresist that can be used to further shape the pedestal of the interconnect bump, many of the applications that are aimed at creating interconnect bumps make use of layers of metal that serve as barrier layers or that have other specific purposes, such as the improvement of adhesion of the various overlying layers or the prevention of diffusion of materials between adjacent layers. These layers collectively form layer 18 of FIG. 2 and have, as is clear from the above, an effect on the shape of the completed bump and are therefore frequently referred to as Ball Limiting Metal (BLM) layer. Frequently used BLM layers are successive and overlying layers of chrome, copper and gold, whereby the chrome is used to enhance adhesion with an underlying aluminum contact pad, the copper layer serves to prevent diffusion of solder materials into underlying layers while the gold layer serves to prevent oxidation of the surface of the copper layer. The BLM layer is represented by layer 18 of FIGS. 2 through 4.
The following paragraphs will provide further details relating to the technologies of electroplating and evaporation as they apply to the processes of forming interconnect bumps.
The method of electroplating follows the processing steps of (over the surface of a substrate wherein a point of electrical contact, typically containing aluminum, has been provided, all steps of processing being centered around this point of electrical contact) depositing a layer of polyimide and etching an opening in this layer of polyimide that aligns with the point of contact, depositing (by vacuum evaporation) a layer of Under Bump Metallurgy (UBM, also referred to as Ball Limiting Metallurgy or BLM) over the layer of poly including the opening created in the layer of poly. A layer of photoresist is deposited over the layer of UBM and patterned, creating an opening in the layer of photoresist that aligns with that part of the layer of UBM that remains in place under the to be created solder bump. Next a layer of metal (typically copper) is electroplated over the layer of photoresist whereby the layer of UBM serves as the common electrode for the electroplating process, the electroplated metal is in contact with the layer of UBM. A layer of solder is next plated over the layer of electroplated metal. The layer of electroplated metal is centered on the opening that has been created in the layer of photoresist, as is the layer of plated solder. The photoresist is removed using the solder bump as a mask, the layer of UBM is selectively etched and removed where this layer does not underlie the to be created solder bump in order to electrically isolate adjacent solder bumps from each other. The critical step of the process is performed as a final step, whereby a flux is applied to the plated solder and the solder is melted in a reflow furnace under a nitrogen atmosphere, creating a spherically shaped solder bump. The above summarized processing steps of electroplating that are used for the creation of a solder bump are supplemented by the step of curing or pre-baking of the layer of photoresist after this layer has been deposited over the layer of UBM.
The process of evaporation also starts with a semiconductor surface wherein a metal point of contact has been provided. A layer of passivation is deposited and patterned, creating an opening in the layer of passivation that aligns with the metal point of contact. A layer of UBM (this layer may be a composite layer of metal such as chromium followed by copper followed by gold in order to promote (with chromium) improved adhesion and to form a diffusion barrier layer or to prevent oxidation (the gold over the copper)) is formed over the layer of passivation and inside the opening created in the layer of passivation. Solder is next selectively plated over the deposited layer of UBM and melted in a solder reflow surface in a hydrogen ambient for solder reflow, in this manner forming the spherically shaped solder bumps.
U.S. Pat. No. 6,057,168 (Seyama et al.) shows a bump process using print screening.
U.S. Pat. No. 5,946,590 (Satoh) shows (in the prior art section) a plating process for bump.
U.S. Pat. No. 5,863,12 (Manteghi) shows a screening printing process for a solder mask for a bump.
U.S. Pat. No. 5,468,655 (Greer) shows a metal paste used in a bump process.
U.S. Pat. No. 5,587,342 (Lin et al.) shows a conductive paste bump process.
U.S. Pat. No. 5,607,099 (Yeh et al.) and U.S. Pat. No. 5,933,752 (Yanagida) show related processes.